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FEATURES 41 MSPS Minimum Sample Rate 80 dB Spurious-Free Dynamic Range 595 mW Power Dissipation Single +5 V Supply On-Chip T/H and Reference Twos Complement Output Format CMOS-Compatible Output Levels APPLICATIONS Cellular/PCS Base Stations GPS Anti-Jamming Receivers Communications Receivers Spectrum Analyzers Electro-Optics Medical Imaging ATE PRODUCT DESCRIPTION
AIN VOFFSET VREF ENCODE ENCODE
12-Bit, 41 MSPS Monolithic A/D Converter AD9042
FUNCTIONAL BLOCK DIAGRAM
AVCC DVCC A1 TH1 TH2 TH3 A2
ADC ADC DAC
+2.4V REFERENCE INTERNAL TIMING
AD9042
7
6 DIGITAL ERROR CORRECTION LOGIC MSB LSB
GND
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
The AD9042 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference are included on chip to provide a complete conversion solution. The AD9042 runs off of a single +5 V supply and provides CMOS-compatible digital outputs at 41 MSPS. Designed specifically to address the needs of wideband, multichannel receivers, the AD9042 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 20 MHz. Noise performance is also exceptional; typical signal-to-noise ratio is 68 dB. The AD9042 is built on Analog Devices' high speed complementary bipolar process (XFCB) and uses an innovative multipass architecture. Units are packaged in a 28-pin DIP; this custom
AD9042AD PIN DESIGNATIONS
GND 1 DVCC 2 GND 3 ENCODE 4 ENCODE 5 GND 6 28 D11 (MSB) 27 D10 26 D9 25 D8
cofired ceramic package forms a multilayer substrate to which internal bypass capacitors and the 9042 die are attached and a 44-pin TQFP low profile surface mount package. The AD9042 industrial grade is specified from -40C to +85C. However, the AD9042 was designed to perform over the full military temperature range (-55C to +125C); consult factory for military grade product options.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 41 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals typ. 80 dBc for -1 dBFS input signals. 3. Low power dissipation: 595 mW off a single +5 V supply. 4. Reference and track-and-hold included on chip. 5. Packaged in 28-pin ceramic DIP and 44-pin TQFP.
AD9042AST PIN DESIGNATIONS
D11 (MSB) DVCC DVCC DVCC DVCC
GND
GND
44 43 42 41 40 39 38 37 36 35 34 DVCC 1 DVCC 2 ENCODE 3 ENCODE 4 GND 5 GND 6 AIN 7 VOFFSET 8 VREF 9 C1 10 AVCC 11 12 13 14 15
AVCC AVCC GND GND
PIN 1
D9
GND
D10
GND
33 D8 32 D7 31 D6 30 D5
AD9042
24 D7
AD9042
TOP VIEW (Not to Scale)
29 D4 28 D3 27 D2 26 D1 25 D0 (LSB) 24 GND 23 NC
TOP VIEW 23 D6 GND 7 (Not to Scale) 22 D5 AIN 8 VOFFSET 9 VREF 10 GND 11 AVCC 12 GND 13 AVCC 14 21 D4 20 D3 19 D2 18 D1 17 D0 (LSB)
AVCC
AVCC
AVCC
15 NC
NC = NO CONNECT
NC = NO CONNECT
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
GND
GND
GND
GND
16 NC
16 17 18 19 20 21 22
AD9042-SPECIFICATIONS
DC SPECIFICATIONS (AV
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Tempco Gain Error Gain Tempco REFERENCE OUT (VREF)2 ANALOG INPUT (AIN) Input Voltage Range Input Resistance Input Capacitance ENCODE INPUT3 Logic Compatibility4 Logic "1" Voltage Logic "0" Voltage Logic "1" Current (VINH = 5 V) Logic "0" Current (VINL = 0 V) Input Capacitance DIGITAL OUTPUTS Logic Compatibility Logic "1" Voltage (IOH = 10 A) Logic "0" Voltage (IOL = 10 A) Output Coding POWER SUPPLY AVCC Supply Voltage I (AVCC) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation Power Supply Rejection (PSRR) Full Full Full Full Full Full +25C Full VI V VI V VI VI I V Full Full Full Full Full +25C VI VI V VI V V
CC
= DVCC = +5 V; VREF tied to VOFFSET through 50 ; TMIN = -40 C, TMAX = +85 C)1
Temp Test Level AD9042AST Min Typ Max 12 Guaranteed 3 +10 25 -6.5 0 +6.5 -50 2.4 VREF 0.500 250 300 5.5 VI VI V VI V V Test Level Min AD9042AD Typ Max 12 Guaranteed 3 +10 25 -6.5 0 +6.5 -50 2.4 VREF 0.500 250 300 7 Units Bits
-10
-10
mV ppm/C % FS ppm/C V V pF
Full +25C
IV V
200
IV V
200
Full Full Full Full +25C
VI VI VI VI V
TTL/CMOS 2.0 5.0 0 0.8 450 625 800 -400 -300 -200 2 CMOS 4.2 0.75
VI VI VI VI V
TTL/CMOS 2.0 5.0 0 0.8 450 625 800 -400 -300 -200 2.5 CMOS 4.2 0.75
V V A A pF
+25C Full +25C Full
I IV I IV
3.5 3.5
0.80 0.85 Twos Complement 5.0 109 5.0 10 119 595 1 5
I IV I IV
3.5 3.5
0.80 0.85 Twos Complement 5.0 109 5.0 10 119 595 1 5
V V V V
-20
147 735 +20
VI V VI V VI VI I V
-20
147 735 +20
V mA V mA mA mW mV/V mV/V
NOTES 1 C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 F capacitor. 2 VREF is normally tied to V OFFSET through 50 . If VREF is used to provide dc offset to other circuits, it should first be buffered. 3 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 F capacitor. 4 ENCODE may also be driven differentially in conjunction with ENCODE; see "Encoding the AD9042" for details. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) ENCODE Pulse Width High ENCODE Pulse Width Low Output Delay (tOD) Temp Full Full +25C +25C +25C +25C Full
(AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 ; TMIN = -40 C, TMAX = +85 C)1
Test Level VI IV V V IV IV IV AD9042AST Min Typ Max 41 5 -250 0.7 10 10 5 9 14 Test Level VI IV V V IV IV IV AD9042AD Min Typ Max 41 5 -250 0.7 10 10 5 9 14 Units MSPS MSPS ps ps rms ns ns ns
NOTE 1 C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 F capacitor.
-2-
REV. A
AC SPECIFICATIONS1
Parameter (Conditions) SNR3 Analog Input @ -1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz SINAD4 Analog Input @ -1 dBFS
(AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 ; TMIN = -40 C, TMAX = +85 C)2
Temp +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full Full Full Full Full Full +25C +25C Full Full +25C +25C +25C Test Level V V V V I V V V V V I V V V V V I V V V V V V V I V V V V V -1.0 AD9042AST Min Typ Max 68 67.5 67.5 67 67 66.5 67.5 67 67.5 67 67 66.5 80 78 80 78 80 78 90 90 90 80 90 0.33 0.3 0.4 0.75 100 10 25 +1.0 Test Level I V I V I V I V I V I V I V I V I V V V V V V V I VI V V V V -1.0 -1.0 Min 65 64.5 64 AD9042AD Typ Max 68 67.5 67.5 67 67 66.5 67.5 67 67.5 67 67 66.5 80 78 80 78 80 78 90 90 90 80 90 0.33 0.3 +1.0 +1.25
AD9042
Units dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBc dBFS LSB rms LSB LSB LSB MHz ns ns
64
1.2 MHz 9.6 MHz 19.5 MHz
64 64 64
64
Worst Spur5 Analog Input @ -1 dBFS
1.2 MHz 9.6 MHz 19.5 MHz
74 74 73
73
Small Signal SFDR (w/Dither)6 Analog Input @1.2 MHz 9.6 MHz 19.5 MHz Two-Tone IMD Rejection7 F1, F2 @ -7 dBFS Two-Tone SFDR (w/Dither)8 Thermal Noise Differential Nonlinearity (ENCODE = 20 MSPS) Integral Nonlinearity (ENCODE = 20 MSPS) Analog Input Bandwidth Transient Response Overvoltage Recovery Time
0.75 100 10 25
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially; see "ENCODING the AD9042" for details. 2 C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 F capacitor. 3 Analog input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). 4 Analog input signal power at -1 dBFS; signal-to-noise and distortion (SINAD ) is the ratio of signal level to total noise + harmonics. 5 Analog input signal power at -1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics. 6 Analog input signal power swept from -20 dBFS to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal (see "Overcoming Static Nonlinearities with Dither"); SFDR is ratio of converter full scale to worst spur. 7 Tones at -7 dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodulation distortion (IMD) rejection is ratio of either tone to worst third order intermod product. 8 Both input tones swept from -20 to -95 dBFS; Dither power = -32.5 dBm; dither circuit used on input signal (see "Overcoming Static Nonlinearities with Dither); two tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur. Specifications subject to change without notice.
REV. A
-3-
AD9042 WAFER TEST LIMITS1 (AV
Parameter POWER SUPPLY ICC Supply Current ENCODE Input Logic "1" Current Logic "0" Current DC ACCURACY Offset Error Gain Error No Missing Codes Differential Nonlinearity @ 5.3 MSPS
CC
= DVCC = +5 V; ENCODE = 10.3 MSPS unless otherwise noted)
Temp +25C +25C +25C +25C +25C +25C +25C AD9042CHIPS Min Max 90 450 -400 -8 -6 147 800 -200 Units mA A A mV % FS LSB
8 6 Guaranteed -0.995
NOTES 1 Electrical test is performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. 2 Die substrate is connected to 0 V.
ABSOLUTE MAXIMUM RATINGS 1
Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current
Min 0 0 0.5 0 -40
Max 7 7 4.5 20 AVCC 4 40
Units V V V mA V V mA
EXPLANATION OF TEST LEVELS Test Level
I II
- -
III - IV - V- VI -
ENVIRONMENTAL2 Operating Temperature Range (Ambient) -40 Maximum Junction Temperature AD9042AD AD9042AST Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) -65
100% production tested. 100% production tested at +25C, and sample tested at specified temperatures. AC testing done on sample basis. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at +25C; sample tested at temperature extremes.
+85 +175 +150 +300 +150
C C C C C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for "D" package (custom ceramic 28-pin DIP): JC = 14C/W; JA = 34C/W. For "ST" package (44-pin TQFP) ; JA = 55C/W.
ORDERING GUIDE
Model AD9042AST AD9042AD AD9042CHIPS AD9042ST/PCB AD9042D/PCB
Temperature Range -40C to +85C (Ambient) -40C to +85C (Ambient) -40C to +85C (Ambient)
Package Description 44-Pin TQFP (Thin Quad Plastic Flatpack) 28-Pin 600 Mil Hermetic Ceramic DIP (DH-28) Unpackaged Die Evaluation Board with AD9042AST Evaluation Board with AD9042AD
Package Option ST-44 DH-28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9042 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD9042
AD9042AST PIN DESCRIPTIONS AD9042AD PIN DESCRIPTIONS
Pin No. Name 1, 2 3 4 DVCC ENCODE ENCODE
Function +5 V Power Supply (Digital). Powers output stage only. Encode input. Data conversion initiated on rising edge. Complement of ENCODE. Drive differentially with ENCODE or bypass to Ground for single-ended clock mode. Ground. Analog Input. Voltage Offset Input. Sets midpoint of analog input range. Normally tied to VREF through 50 resistor. Internal Voltage Reference. Nominally +2.4 V; normally tied to VOFFSET through 50 resistor. Bypass to Ground with 0.1 F + 0.01 F microwave chip cap. Internal Bias Point. Bypass to ground with 0.01 F cap. +5 V Power Supply (Analog). Ground. +5 V Power Supply (Analog). Ground. +5 V Power Supply (Analog). Ground. Ground. No Connects. Ground. Digital Output Bit (Least Significant Bit) Digital Output Bits Ground. +5 V Power Supply (Digital). Powers output stage only. Ground. +5 V Power Supply (Digital). Powers Output Stage only. Digital Output Bits. Digital Output Bit (Most Significant Bit).
Pin No. 1 2 3 4 5
Name GND DVCC GND ENCODE ENCODE
Function Ground. +5 V Power Supply (Digital). Powers output stage only. Ground. Encode input. Data conversion initiated on rising edge. Complement of ENCODE. Drive differentially with ENCODE or bypass to Ground for single-ended clock mode. Ground. Analog Input. Voltage Offset Input. Sets midpoint of analog input range. Normally tied to VREF through 50 resistor. Internal Voltage Reference. Nominally +2.4 V; normally tied to VOFFSET through 50 resistor. Bypass to Ground with 0.1 F cap. Ground. +5 V Power Supply (Analog). Ground. +5 V Power Supply (Analog). No Connects. Digital Output Bit. (Least Significant Bit). Digital Output Bits. Digital Output Bit (Most Significant Bit).
5, 6 7 8
GND AIN VOFFSET
6, 7 8 9
GND AIN VOFFSET
9
VREF
10
VREF
10 11, 12 13, 14 15, 16 17, 18 19, 20 21 22 23 24 25 26-33 34, 35 36, 37 38, 39 40, 41 42, 43 44
C1 AVCC GND AVCC GND AVCC GND GND NC GND D0 (LSB) D1-D8 GND DVCC GND DVCC D9-D10 D11 (MSB)1
11 12 13 14 15, 16 17 18-27 28
GND AVCC GND AVCC NC D0 (LSB) D1-D10 D11 (MSB)1
NOTE 1 Output coded as twos complement.
AD9042 CUSTOM 28-PIN DIP PACKAGE
NOTE 1 Output coded as twos complement.
REV. A
-5-
AD9042
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . 155 x 168 x 21 ( 1) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,605 Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
DIE LAYOUT W/PAD LABELS
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal 150% of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
DEFINITION OF SPECIFICATIONS Analog Bandwidth Spurious-Free Dynamic Range
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Transient Response
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input.
Two-Tone Intermodulation Distortion Rejection
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
-6-
REV. A
Equivalent Circuits-AD9042
N
tA = -250 PS TYP
ANALOG INPUT (AIN) ENCODE INPUTS (ENCODE) DIGITAL OUTPUTS (D11-D0) N-2 N-1 N N+1
tOD = 9ns TYP
Figure 1. Timing Diagram
AVCC +3.5V
CURRENT MIRROR DVCC
AVCC
250A 250
250
AIN AVCC 250A +1.5V VOFFSET 200 6pF
VREF D0-D11 DVCC
Figure 2. Analog Input Stage
CURRENT MIRROR
AVCC
AVCC
R1 17k
R1 17k
AVCC
Figure 5. Digital Output Stage
ENCODE
ENCODE R2 8k TIMING CIRCUITS R2 8k
AVCC AVCC 2.4V VREF
Figure 3. Encode Inputs
0.5mA
AVCC
Figure 6. 2.4 V Reference
+5V
+5V 10k
VREF AVCC AVCC
0.1F 200kHz SINEWAVE 49.9 8 9 AIN
2,12,14 D11 28
VOFFSET VREF ENCODE ENCODE D0
CURRENT MIRROR C1 (PIN 10*)
10 4 5
TTL CLOCK OSC. NC
*AD9042AST ONLY
INTERNAL NODE ON AD9042AD
17
1,3,6,7,11,13
Figure 4. Compensation Pin, C1
NOTE: ALL +5V SUPPLY PINS & VREF PIN BYPASSED TO GND WITH A 0.1F CAPACITOR. PINS 15,16 ARE NOT CONNECTED.
Figure 7. AD9042AD Burn-In Diagram
REV. A
-7-
AD9042-Typical Performance Characteristics
0
POWER RELATIVE TO ADC FULL SCALE - dB
ENCODE = 41 MSPS AIN = 1.2MHz -20
81 T = +25C
ENCODE = 41 MSPS TEMP = -40C, +25C, & +85C
WORST CASE HARMONIC - dBc
-40
80
T = -40C T = +85C
-60 2 -80 3 4 5 6 7 8 9
79
78
-100
77
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
0
2
4
6 8 10 12 14 16 ANALOG INPUT FREQUENCY - MHz
18
20
Figure 8. Single Tone at 1.2 MHz
Figure 11. Harmonics vs. AIN
0
POWER RELATIVE TO ADC FULL SCALE - dB
ENCODE = 41 MSPS AIN = 9.6MHz -20
70
ENCODE = 41 MSPS TEMP = -40C, +25C, & +85C
69
-40
SNR - dB
T = -40C 68 T = +25C 67 T = +85C
-60 4 -80 88 5 3 7 6 2
-100
66
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
0
2
4
6 8 10 12 14 16 ANALOG INPUT FREQUENCY - MHz
18
20
Figure 9. Single Tone at 9.6 MHz
Figure 12. Noise vs. AIN
0
90 ENCODE = 41 MSPS
ENCODE = 41 MSPS AIN = 19.5MHz
POWER RELATIVE TO ADC FULL SCALE - dB
-20
80
WORST HARMONIC - dBc
-40
70
-60 2 -80 4 6 8 9 7 5 3
60
50
-100
40
-120 dc
30
4.1 8.2 12.3 FREQUENCY - MHz 16.4 20.5
1
2
10 4 20 40 ANALOG INPUT FREQUENCY - MHz
100
Figure 10. Single Tone at 19.5 MHz
Figure 13. Harmonics vs. AIN
-8-
REV. A
AD9042
0
85
ENCODE = 41 MSPS AIN = 15.3, 19.5MHz SNR, WORST CASE SPURIOUS - dB, dBc
POWER RELATIVE TO ADC FULL SCALE - dB
AIN = 4.3MHz WORST SPUR 80
-20
-40
75
-60
70 SNR
-80
-100
65
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
60 dc
5
10
15
20 25 30 35 SAMPLE RATE - MSPS
40
45
50
Figure 14. Two Tones at 15.3 MHz & 19.5 MHz
Figure 17. SNR, Worst Harmonic vs. Encode
100
90
SNR, WORST FULL SCALE SPURIOUS - dBc
WORST CASE SPURIOUS - dBc AND dBFS
90 80 70 60 50 40 dBc 30 20 10 0 -80 -70 ENCODE = 41 MSPS AIN = 19.5MHz
dBFS
85 80 75 70 65 60 55 50 45 40 35 30 25 30 35 SNR WORST SPUR
ENCODE = 41 MSPS AIN = 19.5MHz
SFDR = 80dB REFERENCE LINE
-60 -50 -40 -30 -20 ANALOG INPUT POWER LEVEL - dBFS
-10
0
40 45 50 55 60 ENCODE DUTY CYCLE - %
65
70
75
Figure 15. AD9042AD Single Tone SFDR
Figure 18. SNR, Worst Spurious vs. Duty Cycle
100
WORST CASE SPURIOUS - dBc AND dBFS
0
90 80 70 60 50 40 30 20 10 0 -80 -70 -60 -50 -40 -30 -20 INPUT POWER LEVEL (F1 = F2) - dBFS -10 0 ENCODE = 41 MSPS F1 = 19.3MHz F2 = 19.51MHz SFDR = 80dB REFERENCE LINE
POWER RELATIVE TO ADC FULL SCALE - dB
ENCODE = 41 MSPS AIN = BROADBAND_NOISE -20
-40
-60 4 -80
-100
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
Figure 16. AD9042AD Two Tone SFDR
Figure 19. NPR Output Spectrum
REV. A
-9-
AD9042
0 0
POWER RELATIVE TO ADC FULL SCALE - dB
POWER RELATIVE TO ADC FULL SCALE - dB
-20
ENCODE = 41 MSPS AIN = 19.5MHz @ -29 dBFS NO DITHER
-20
ENCODE = 41 MSPS AIN = 19.5MHz @ -29 dBFS DITHER = -32.5dBm
-40
-40
-60
-60
-80
2
4
6
8
8
7
5
3
-80
2
4
6
8
8
7
5
3
-100
-100
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
Figure 20. 4K FFT without Dither
Figure 23. 4K FFT with Dither
100 90
WORST CASE SPURIOUS - dBc WORST CASE SPURIOUS - dBc
100 ENCODE = 41 MSPS AIN = 19.5MHz NO DITHER 90 80 70 60 50 40 30 20 10 0 0 -80 -70 SFDR = 80dB REFERENCE LINE -60 -50 -40 -30 -20 -10 ANALOG INPUT POWER LEVEL - dBFS 0 ENCODE = 41 MSPS AIN = 19.5MHz DITHER = -32.5dBm
80 70 60 50 40 30 20 10 0 -80
SFDR = 80dB REFERENCE LINE -70 -60 -50 -40 -30 -20 -10 ANALOG INPUT POWER LEVEL - dBFS
Figure 21. SFDR without Dither
Figure 24. SFDR with Dither
0
POWER RELATIVE TO ADC FULL SCALE - dB POWER RELATIVE TO ADC FULL SCALE - dB
0 ENCODE = 41 MSPS AIN = 2.5MHz @ -26 dBFS NO DITHER ENCODE = 41 MSPS AIN = 2.5MHz@-26dBFS DITHER = -32.5dBm
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
Figure 22. 128K FFT without Dither
Figure 25. 128K FFT with Dither
-10-
REV. A
AD9042
THEORY OF OPERATION
The AD9042 analog-to-digital converter (ADC) employs a twostage subrange architecture. This design approach ensures 12-bit accuracy, without the need for laser trim, at low power. As shown in the functional block diagram, the 1 V p-p singleended analog input, centered at 2.4 V, drives a single-in to differential-out amplifier, A1. The output of A1 drives the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of the 6-bit coarse ADC. The digital output of the coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit DAC is subtracted from the delayed analog signal at the input to TH3 to generate a residue signal. TH2 is used as an analog pipeline to null out the digital delay of the coarse ADC. The residue signal is passed to TH3 on a subsequent clock cycle where the signal is amplified by the residue amplifier, A2, and converted to a digital word by the 7-bit residue ADC. One bit of overlap is used to accommodate any linearity errors in the coarse ADC. The 6-bit coarse ADC word and 7-bit residue word are added together and corrected in the digital error correction logic to generate the output word. The result is a 12-bit parallel digital word which is CMOS-compatible, coded as twos complement.
APPLYING THE AD9042 Encoding the AD9042
V1 =
5R2 RX to lower logic threshold. R1R2 + R1RX + R2 RX
ENCODE SOURCE
ENCODE
+5V R1
Vl
0.01F RX
ENCODE R2
AD9042
Figure 27. Lower Logic Threshold for Encode
V1 =
5R2 RR R2 + 1 X R1 + RX
to raise logic threshold.
AVCC RX ENCODE SOURCE +5V ENCODE R1 ENCODE R2
Vl
0.01F
AD9042
Figure 28. Raise Logic Threshold for Encode
The AD9042 is designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s) must be clean and free from jitter. Sources with excessive jitter will limit SNR (ref. Equation 1 under "Noise Floor and SNR").
AD9042
TTL OR CMOS SOURCE ENCODE ENCODE 0.01F
While the single-ended encode will work well for many applications, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is not recommended that differential TTL logic be used however, because most TTL families that support complementary outputs are not delay or slew rate matched. Instead, it is recommended that the encode signal be ac-coupled into the ENCODE and ENCODE pins. The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 ohms, to the primary side of an RF transformer (these transformers are inexpensive and readily available; part# in Figure 29 is from Mini-Circuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs are self biased, no additional components are required.
Figure 26. Single-Ended TTL /CMOS Encode
The AD9042 encode inputs are connected to a differential input stage (see Figure 3 under EQUIVALENT CIRCUITS). With no input connected to either the ENCODE or input, the voltage dividers bias the inputs to 1.6 volts. For TTL or CMOS usage, the encode source should be connected to ENCODE. ENCODE should be decoupled using a low inductance or microwave chip capacitor to ground. Devices such as AVX 05085C103MA15, a 0.01 F capacitor, work well. If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor, RX, to raise or lower the trip point (see Figure 3; R1 = 17k, R2 = 8k).
100 TTL
T1-1T
ENCODE
AD9042
ENCODE
Figure 29. TTL Source - Differential Encode
REV. A
-11-
AD9042
If no TTL source is available, a clean sine wave may be substituted. In the case of the sine source, the matching network is shown below. Since the matching transformer specified is a 1:1 impedance ratio, R, the load resistor should be selected to match the source impedance. The input impedance of the AD9042 is negligible in most cases.
T1-1T R ENCODE
amplifier offset; this reference is designed to track internal circuit shifts over temperature.
250 250 AIN
SINE SOURCE
ENCODE
AD9042
VOFFSET TIED TO VREF THROUGH 50 OHMS
50 +2.4V REFERENCE 0.1F
AD9042
Figure 33. Analog Input Offset by +2.4 V Reference Figure 30. Sine Source - Differential Encode
If a low jitter ECL clock is available, another option is to accouple a differential ECL signal to the encode input pins as shown below. The capacitors shown here should be chip capacitors but do not need to be of the low inductance variety.
0.1F ENCODE ECL GATE 0.1F ENCODE 510 510
AD9042
Although the AD9042 may be used in many applications, it was specifically designed for communications systems which must digitize wide signal bandwidths. As such, the analog input was designed to be ac-coupled. Since most communications products do not down-convert to dc, this should not pose a problem. One example of a typical analog input circuit is shown below. In this application, the analog input is coupled with a high quality chip capacitor, the value of which can be chosen to provide a low frequency cutoff that is consistent with the signal being sampled; in most cases, a 0.1 F chip capacitor will work well.
ANALOG SIGNAL SOURCE RT 0.1F AIN VOFFSET 50 VREF 0.1F
AD9042
-VS
Figure 31. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal.
AD96687 (1/2)
0.1F ENCODE 50 510 0.1F ENCODE 510
Figure 34. AC-Coupled Analog Input Signal
AD9042
-VS
Figure 32. ECL Comparator for Encode
Another option for ac-coupling is a transformer. The impedance ratio and frequency characteristics of the transformer are determined by examining the characteristics of the input signal source (transformer primary connection), and the AD9042 input characteristics (transformer secondary connection). "RT" should be chosen to satisfy termination requirements of the source, given the transformer turns ratio. A blocking capacitor is required to prevent AD9042 dc bias currents from flowing through the transformer.
BPF ANALOG SIGNAL SOURCE XFMR RT 50 LO 0.1F VREF 0.1F AIN VOFFSET
Care should be taken not to overdrive the encode input pin when ac coupled. Although the input circuitry is electrically protected from over or under voltage conditions, improper circuit operations may result from overdriving the encode input pins.
Driving the Analog Input
AD9042
Because the AD9042 operates off of a single +5 V supply, the analog input range is offset from ground by 2.4 volts. The analog input, AIN, is an operational amplifier configured in an inverting mode (ref. Equivalent Circuits: Analog Input Stage). VOFFSET is the noninverting input which is normally tied through a 50 ohm resistor to VREF (ref. Equivalent Circuits: 2.4 V Reference). Since the operational amplifier forces its inputs to the same voltage, the inverting input is also at 2.4 volts. Therefore, the analog input has a Thevenin equivalent of 250 ohms in series with a 2.4 volt source. It is strongly recommended that the AD9042's internal voltage reference be used for the
Figure 35. Transformer-Coupled Analog Input Signal
When calculating the proper termination resistor, note that the external load resistor is in parallel with the AD9042 analog input resistance, 250 ohms. The external resistor value can be calculated from the following equation: RT = 1 1 1 - Z 250 where Z is desired impedance.
-12-
REV. A
AD9042
A dc-coupled input configuration (shown below) is limited by the drive amplifier performance. The AD9042's on-chip reference is buffered using the OP279 dual, rail-to-rail operational amplifier. The resulting voltage is combined with the analog source using an AD9631. Pending improvements in drive amplifiers, this dc-coupled approach is limited to ~75 dB-80 dB of dynamic performance depending on which drive amplifier is used. The AD9631 and OP279 run off 5 V.
SIGNAL SOURCE 21 200 79 0.1F 1k 571 0.1F 114 0-50pF VOFFSET 49.9 VREF
Layout Information
AD9631
50
AD9042
AIN
The schematic of the evaluation boards (Figures 37 and 38) represents a typical implementation of the AD9042. The pinout of the AD9042 facilitates ease of use and the implementation of high frequency/high resolution design practices. All of the digital outputs are on one side of the packages while the other sides contain all of the inputs. It is highly recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. Depending on the configuration used for the encode and analog inputs, one or more capacitors are required on those input pins. The capacitors used on the ENCODE and VREF pins must be a low inductance chip capacitor as referenced previously in the data sheet. Although a multilayer board is recommended, it is not required to achieve good results. As shown in the DIP evaluation board layout (Figures 39-42), the top layer forms a near solid ground plane while the under side is used for routing signal. No vias or jumpers are required to route signals in and out of the AD9042AD. Each supply is decoupled to ground directly at the device. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate (broken only by the insertion of the series resistor). Logic fanout for each bit should be one CMOS gate.
Evaluation Boards
OP279 (1/2)
OP279 (1/2)
Figure 36. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. Linear supplies are strongly recommended as switching supplies tend to have radiated components that may be "received" by the AD9042. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD9042 has separate digital and analog +5 V pins. The analog supplies and the denoted AVCC digital supply pins are denoted DVCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching noise back into the analog supplies. Note that AVCC must be held within 5% of 5 volts, however the DVCC supply may be varied according to output digital logic family (i.e., DVCC should be connected to the supply for the digital circuitry).
Output Loading
The evaluation board for the AD9042 is very straight forward consisting of power, signal inputs and digital outputs. The evaluation board includes an onboard clock oscillator for the encode; all the user must supply is power and an analog signal. Power to the analog supply pins is connected via banana jacks. The analog supply powers the crystal oscillator and the AVCC pins of the AD9042. The DVCC power is supplied via J3, the digital interface. This digital supply connection also powers the digital gates on the PCB. By maintaining separate analog and digital power supplies, degradation in SNR and SFDR is kept to a minimum. Total power requirement for either PCB is approximately 140 mA. This configuration allows for easy evaluation of different logic families (i.e., connection to a 3.3 volt logic board). The analog input is connected via J2 and is capacitively coupled to the AD9042 (see "Driving the Analog Input"). The onboard termination resistor is 60.4 . This resistor in parallel with AD9042's input resistance (250 ) provides a 50 load to the analog source. If a different input impedance is required, replace R1 by using the following equation 1 R1 = 1 1 where Z is desired input impedance. - Z 250 The analog input range of PCB is 0.5 volts (i.e., signal accoupled to AD9042). The encode signal is generated using the onboard crystal oscillator, U1. The oscillator is socketed and may be replaced by an external encode source via J1. If an external source is used, it should be a high quality TTL source. A transformer converts the single-ended TTL signal to a differential clock (see "Encoding the AD9042"). Since the encode is coupled with a -13-
Care must be taken when designing the data receivers for the AD9042. It is recommended that the digital outputs drive a series resistor of 499 ohms followed by a CMOS gate like the 74AC574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematics shown in Figures 37 and 38. The digital outputs of the AD9042 have a unique constant slew rate output stage. The output slew rate is about 1 V/ns independent of output loading. A typical CMOS gate combined with PCB trace and through hole will have a load of approximately 10 pF. Therefore as each bit switches, 10 mA
1V 10 pF x 1ns of dynamic current per bit will flow in or out of
the device. A full- scale transition can cause up to 120 mA (12 bits x 10 mA/bit) of current to flow through the digital output stage. The series resistor will minimize the output currents that can flow in the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD9042.
REV. A
AD9042
transformer, a sine wave could have been used; however, note that U5 requires TTL levels to function properly. AD9042 output data is latched using 74ACT574 (U3, U4) latches following 499 ohm series resistors. The resistors limit the current that would otherwise flow due to the digital output slew rate. The resistor value was chosen to represent a time constant of ~25% of the data rate at 40 MHz. This reduces slew rate while not appreciably distorting the data waveform. Data is latched in a pipeline configuration; a rising edge generates the new AD9042 data sample, latches the previous data at the converter output, and strobes the external data register over J3. Power and ground must be applied to J3 to power the digital logic section of the evaluation board.
+5VA C14 0.1F 14 8 U1 K1115 OUT VEE 7 BNC J1 VCC
U5 74AS00
1 2 3
U5 74AS00
4 5 6 BUFLAT R2 499
U3 74ACT574
9 8 7 6 R3 499 R4 499 5 R5 499 4 R6 499 R7 499 3 GND GND 2 8D 7D 6D 5D 4D 3D 2D 1D CK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 +5V B11 B10 B09 B08 B07 B06 B05 B04 BUFLAT B03 B02 B01 R13 499 B06 B07 B08 B09 B10 B11
R15 100
T1 T1-1T 3 4 2 6 1 GND 1 GND
U2 AD9042
(MSB) D11 28 D10 27 D9 26 D8 25 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 (LSB) D0 17 NC 16 NC 15 R9 499
H40DM J3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
+5V 2 DVCC GND 3 GND 4 ENCODE 5 ENCODE GND 6 GND
C2 0.1F BNC J2 R1 60.4
GND 7 GND 8 AIN 9 VOFFSET R14 49.9 C3 0.1F 10 VREF GND 11 GND +5VA 12 AVCC GND 13 GND +5VA 14 AVCC
U4 74ACT574
9 8 7 6 5 8D 7D 6D 5D 4D 3D 2D 1D CK 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 B00 B01 B02 B03 B04 B05
B00 GND GND GND GND GND
NC = NO CONNECT R8 499
R10 499
R11 499
R12 499
+5V + C6 10F C7 0.1F C11 0.1F C12 0.1F C13 0.1F C15 0.1F C16 0.1F GND GND +5VA + C4 10F C8 0.1F C9 0.1F C17 0.1F
4 3 2
11
Figure 37. AD9042D/PCB Schematic
Table I. AD9042D/PCB Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Quantity 2 10 2 1 2 1 12 1 1 1 1 1 2 1
Reference +5VA, GND C2-C3, C7-C9, C11-C17 C4, C6 J3 J1, J2 R1 R2-R13 R14 R15 T1 U1 U2 U3, U4 U5
Description Banana Jack Ceramic Chip Capacitor 0805, 0.1 F Tantalum Chip Capacitor 10 F 40-Pin Double Row Male Header BNC Coaxial PCB Connector Surface Mount Resistor 1206, 60.4 ohms Surface Mount Resistor 1206, 499 ohms Surface Mount Resistor 1206, 49.9 ohms Surface Mount Resistor 1206, 100 ohms Surface Mount Transformer Mini-Circuits T1-1T 40.96 MHz Clock Oscillator AD9042AD 12-Bit-41 MSPS ADC Converter 74ACT574 Octal Latch 74AS00 Quad Two Input NAND Gate -14- REV. A
AD9042
U3 74ACT574 U5 74AS00
1 +5VA C14 0.1F 14 2 3
U5 74AS00
4 5 6 BUFLAT R5 499 R6 499 R7 499 R2 499 R3 499 GND GND R4 499
9 8 7 6 5 4 3 2
8D 7D 6D 5D 4D 3D 2D 1D CK 11 1
8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE
12 13 14 15 16 17 18 19
B06 B07 B08 B09 B10 B11
GND
GND
GND
GND
+5V
+5V
VEE
D11
+5V
+5V
U1 K1115
BNC J1
VCC OUT 7 8
H40DM J3
+5V B11 B10 B09 B08 B07 B06 B05 B04 1 2 3 4 5 6 7 8 9 10 11 B03 12 B02 13 B01 14 B00 15 GND 16 GND 17 GND 18 GND 19 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
D9
DVCC
D10
DVCC
GND
GND
DVCC
DVCC
GND
GND
D8 D7 D6 D5 D4
R15 100
T1 T1-1T 3 4 2 6 1:1 1 +5V +5V
44 43 42 41 40 39 38 37 36 35 34 1 DVCC 2 DVCC 3 ENCODE 4 ENCODE GND 5 GND 6 GND 7 AIN 33 32 31 30 29 28 27 26 25 24 GND 23
BNC J2
C2 0.1F
GND
U2 AD9042
D3 D2 D1 D0 GND
BUFLAT
R1 60.4 R14 49.9
8 VOFFSET 9
VREF
10 C1
AVCC AVCC AVCC AVCC GND GND AVCC GND GND GND
R13 499 R12 499 R11 499 R10 499 9 8 7 6 5 R9 499
+5VA
+5VA
GND
+5VA
+5VA
GND
GND
GND
+5VA
GND
GND
C18 0.01F
C3 0.1F
C1 0.01F
12 13 14 15
16 17 18 19 20 21 22
GND
+5VA 11
AVCC
NC
U4 74ACT574
8D 7D 6D 5D 4D 3D 2D 1D CK 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 B00 B01 B02 B03 B04 B05
GND 20
NC = NO CONNECT GND1 +5VA +5VA GND GND +5V + C6 10F C7 0.1F C11 0.1F C12 0.1F C13 0.1F C15 0.1F C16 0.1F
R8 499
4 GND GND 3 2
11
+5VA + C4 10F C8 0.1F C9 0.1F C17 0.1F
Figure 38. AD9042ST/PCB Schematic
Table II. AD9042ST/PCB Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 REV. A
Quantity 2 10 2 1 2 1 12 1 1 1 1 1 2 1 1
Reference +5VA, GND C2-C3, C7-C9, C11-C17 C4, C6 J3 J1, J2 R1 R2-R13 R14 R15 T1 U1 U2 U3, U4 U5 C1, C18
Description Banana Jack Ceramic Chip Capacitor 0805, 0.1 F Tantalum Chip Capacitor 10 F 40-Pin Double Row Male Header BNC Coaxial PCB Connector Surface Mount Resistor 1206, 60.4 ohms Surface Mount Resistor 1206, 499 ohms Surface Mount Resistor 1206, 49.9 ohms Surface Mount Resistor 1206, 100 ohms Surface Mount Transformer Mini-Circuits T1-1T 40.96 MHz Clock Oscillator AD9042AST 12-Bit-41 MSPS ADC Converter 74ACT574 Octal Latch 74AS00 Quad Two Input NAND Gate Ceramic Chip Capacitor 0805, 0.01 F AVX05085C103MA15 -15-
AD9042
C14 M4 U1 J1 C12 U5 U3 J3 M3
ENC
GND
AD9042 PIN 1
C7 U2
C13
GND +5VA
+5VA J2 R14 C3 C9
U4
AIN
MICROPHONE M1
C8 GND1
TO ANTENNATM
AD9042D/PCB EVALUATION 48391
a
1995 (c) USA JB8/KU8 6 / 6 / 95
C11
M2
Figure 39. AD9042D/PCB Top Side Silk Screen
Figure 41. AD9042D/PCB Top Side Copper (Negative)
C6 R7 R6 R5 R4 R3 R2 R8 R9 R10 R11 R12 R13 C4 R15
C2 T1 R1
Figure 40. AD9042D/PCB Bottom Side Silk Screen
Figure 42. AD9042D/PCB Bottom Side Copper (Negative)
-16-
REV. A
AD9042
C18
Figure 43. AD9042ST/PCB Top Side Silk Screen
Figure 45. AD9042ST/PCB Top Side Copper (Negative)
Figure 44. AD9042ST/PCB Bottom Side Silk Screen
Figure 46. AD9042ST/PCB Bottom Side Copper (Positive)
REV. A
-17-
AD9042
+5VA
+5V
Figure 47. AD9042ST/PCB Grounded Layer (Negative)
Figure 48. AD9042ST/PCB "Split" Power Layer (Negative)
-18-
REV. A
AD9042
DIGITAL WIDEBAND RECEIVERS Introduction
Several key technologies are now being introduced that may forever alter the vision of radio. Figure 49 shows the typical dual conversion superheterodyne receiver. The signal picked up by the antenna is mixed down to an intermediate frequency (IF) using a mixer with a variable local oscillator (LO); the variable LO is used to "tune-in" the desired signal. This first IF is mixed down to a second IF using another mixer stage and a fixed LO. Demodulation takes place at the second or third IF using either analog or digital techniques.
NARROWBAND FILTER NARROWBAND FILTER ADCs I Q
is used for demodulation, different routines may be used to demodulate different standards such as AM, FM, GMSK or any other desired standard. In addition, as new standards arise or new software revisions are generated, they may be field installed with standard software update channels. A radio that performs demodulation in software as opposed to hardware is often referred to as a soft radio because it may be changed or modified simply through code revision.
System Description
LNA
RF e.g. 900MHz
IF1
IF2
VARIABLE
FIXED
SHARED
ONE RECEIVER PER CHANNEL
In the wideband digital radio (Figure 50), the first down conversion functions in much the same way as a block converter does. An entire band is shifted in frequency to the desired intermediate frequency. In the case of cellular base station receivers, 5 MHz to 20 MHz of bandwidth are down-converted simultaneously to an IF frequency suitable for digitizing with a wideband analog-to-digital converter. Once digitized the broadband digital data stream contains all of the in-band signals. The remainder of the radio is constructed digitally using special purpose and general purpose programmable DSP to perform filtering, demodulation and signal conditioning not unlike the analog counter parts. In the narrowband receiver (Figure 49), the signal to be received must be tuned. This is accomplished by using a variable local oscillator at the first mix down stage. The first IF then uses a narrow band filter to reject out of band signals and condition the selected carrier for signal demodulation. In the digital wideband receiver (Figure 50), the variable local oscillator has been replaced with a fixed oscillator, so tuning must be accomplished in another manner. Tuning is performed digitally using a digital down conversion and filter chip frequently called a channelizer. The term channelizer is used because the purpose of these chips is to select one channel out of the many within the broadband of spectrum actually present in the digital data stream of the ADC.
DECIMATION FILTER COS DATA DIGITAL TUNER SIN DECIMATION FILTER LOW-PASS FILTER LOW-PASS FILTER I
Figure 49. Narrowband Digital Receiver Architecture
If demodulation takes place in the analog domain then traditional discriminators, envelop detectors, phase locked loops or other synchronous detectors are generally employed to strip the modulation from the selected carrier. However, as general purpose DSP chips such as the ADSP-2181 become more popular, they will be used in many basebandsampled applications like the one shown in Figure 49. As shown in the figure, prior to ADC conversion, the signal must be mixed down, filtered, and the I and Q components separated. These functions are realizable through DSP techniques, however several key technology breakthroughs are required: high dynamic range ADCs such as the AD9042, new DSPs (highly programmable with onboard memory, fast), digital tuner & filter (with programmable frequency and BW) and wide band mixers (high dynamic range with >12.5 MHz BW).
WIDEBAND FILTER WIDEBAND ADC
LNA
WIDEBAND MIXER
Q
RF e.g. 900MHz
"n" CHANNELS TO DSP 12.5MHz (416 CHANNELS) FIXED SHARED CHANNEL SELECTION
Figure 51. Digital Channelizer
Figure 50. Wideband Digital Receiver Architecture
Figure 50 shows such a wideband system. This design shows that the front end variable local oscillator has been replaced with a fixed oscillator (for single band radios) and the back end has been replaced with a wide dynamic range ADC, digital tuner and DSP. This technique offers many benefits. First, many passive discrete components have been eliminated that formed the tuning and filtering functions. These passive components often require "tweaking" and special handling during assembly and final system alignment. Digital components require no such adjustments; tuner and filter characteristics are always exactly the same. Moreover, the tuning and filtering characteristics can be changed through software. Since software REV. A
Figure 51 shows the block diagram of a typical channelizer. Channelizers consist of a complex NCO (Numerically Controlled Oscillator), dual multiplier (mixer), and matched digital filters. These are the same functions that would be required in an analog receiver, however implemented in digital form. The digital output from the channelizer is the desired carrier, frequently in I & Q format; all other signals have been filtered and removed based on the filtering characteristics desired. Since the channelizer output consists of one selected RF channel, one tuner chip is required for each frequency received, although only one wideband RF receiver is needed for the entire band. Data from the channelizer may then be processed using a digital signal processor such as the ADSP2181 or the SHARC processor, the ADSP-21062. This data may then be processed through software to demodulate the information from the carrier.
-19-
AD9042
+5V (A) PRESELECT FILTER LNA 5-15MHz PASSBAND AIN LO DRIVE 864MHz M/N PLL SYNTHESIZER 40.96MHz REFERENCE CLOCK REF IN D11 I&Q DATA +5V (D) 499 CMOS BUFFER CHANNELIZER (REF. FIG 51)
ADSP-2181
AD9042
ENCODE ENCODE
12
NETWORK CONTROLLER INTERFACE
D0
CLK
Figure 52. Simplified 5 MHz Wideband "A" Carrier Receiver
System Requirements
Figure 52 shows a typical wideband receiver subsystem based around the AD9042. This strip consists of a wideband IF filter, amplifier, ADC, latches, channelizer and interface to a digital signal processor. This design shows a typical clocking scheme used in many receiver designs. All timing within the system is referenced back to a single clock. While this is not necessary, it does facilitate PLL design, ease of manufacturing, system test, and calibration. Keeping in mind that the overall performance goal is to maintain the best possible dynamic range, many considerations must be made. One of the biggest challenges is selecting the amplifier used to drive the AD9042. Since this is a communications application, the key specification for this amplifier is spurious-free dynamic range, or SFDR. An amplifier should be selected that can provide SFDR performance better than 80 dB into 250 ohms. One such amplifier is the AD9631. These low spurious levels are necessary as harmonics due to the drive amplifier and ADC could distort the desired signals of interest. Two other key considerations for the digital wideband receiver are converter sample rate and IF frequency range. Since performance of the AD9042 converter is nearly independent of both sample rate and analog input frequency (Figures 11, 12, and 17), the designer has greater flexibility in the selection of these parameters. Also, since the AD9042 is a bipolar device, power dissipation is not a function of sample rate. Thus there is no penalty paid in power by operating at faster sample rates. All of this is good, because by carefully selecting input frequency range and sample rate, the drive amplifier and ADC harmonics can actually be placed out-of-band. Thus other components such as filters and IF amplifiers may actually end up being the limiting factor on dynamic range. For example, if the system has second and third harmonics that are unacceptably high, by carefully selecting the encode rate and signal bandwidth, these second and third harmonics can be placed out-of-band. For the case of an encode rate equal to 40.96 MSPS and a signal bandwidth of 5.12 MHz, placing the fundamental at 5.12 MHz places the second and third harmonics out of band as shown in the table below.
Table III.
Another option can be found through bandpass sampling. If the analog input signal range is from dc to FS/2, then the amplifier and filter combination must perform to the specification required. However, if the signal is placed in the third Nyquist zone (FS to 3 FS/2), the amplifier is no longer required to meet the harmonic performance required by the system specifications since all harmonics would fall outside the passband filter. For example, the passband filter would range from FS to 3 FS/2. The second harmonic would span from 2 FS to 3 FS, well outside the passband filter's range. The burden then has been passed off to the filter design provided that the ADC meets the basic specifications at the frequency of interest. In many applications, this is a worthwhile tradeoff since many complex filters can easily be realized using SAW and LCR techniques alike at these relatively high IF frequencies. Although harmonic performance of the drive amplifier is relaxed by this technique, intermodulation performance cannot be sacrificed since intermods must be assumed to fall in-band for both amplifiers and converters.
Noise Floor and SNR
Oversampling is the act of sampling at a rate that is greater than twice the bandwidth of the signal desired. Oversampling does not have anything to do with the actual frequency of the sampled signal, it is the bandwidth of the signal that is key. Bandpass or "IF" sampling refers to sampling a frequency that is higher than Nyquist and often provides additional benefits such as down conversion using the ADC and track-and-hold as a mixer. Oversampling leads to processing gains because the faster the signal is digitized, the wider the distribution of noise. Since the integrated noise must remain constant, the actual noise floor is lowered by 3 dB each time the sample rate is doubled. The effective noise density for an ADC may be calculated by the equation:
V NOISE rms / Hz = 10 - SNR /20 4 FS
For a typical SNR of 68 dB and a sample rate of 40.96 MSPS, this is equivalent to 31 nV / Hz . This equation shows the relationship between SNR of the converter and the sample rate FS. This equation may be used for computational purposes to determine overall receiver noise. The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on three terms. These are jitter, average DNL error and thermal noise. Each of these terms contributes to the noise within the converter.
Encode Rate Fundamental Second Harmonic Third Harmonic
40.96 MSPS 5.12 MHz-10.24 MHz 10.24 MHz-20.48 MHz 15.36 MHz-10.24 MHz
-20-
REV. A
AD9042
Equation 1:
2 2 VNOISE rms 2 1+ SNR = -20 log 2 FANALOG t J rms + 12 + 212 2 FANALOG = analog input frequency = rms jitter of the encode (rms sum of encode source t J rms and internal encode circuitry) = average DNL of the ADC VNOISE rms = V rms thermal noise referred to the analog input of the ADC 1/2
(
)
linearity to appear as if it were random. Then, the average linearity over the range of dither will dominate SFDR performance. In the AD9042, the repetitive cycle is every 15.625 mV p-p. To insure adequate randomization, 5.3 mV rms is required; this equates to a total dither power of -32.5 dBm. This will randomize the DNL errors over the complete range of the residue converter. Although lower levels of dither such as that from previous analog stages will reduce some of the linearity errors, the full effect will only be gained with this larger dither. Increasing dither even more may be used to reduce some of the global INL errors. However, signals much larger than the mVs proposed here begin to reduce the usable dynamic range of the converter. Even with the 5.3 mV rms of noise suggested, SNR would be limited to 36 dB if injected as broadband noise. To avoid this problem, noise may be injected as an out-of-band signal. Typically, this may be around dc but may just as well be at FS/2 or at some other frequency not used by the receiver. The bandwidth of the noise is several hundred kilohertz. By band-limiting and controlling its location in frequency, large levels of dither may be introduced into the receiver without seriously disrupting receiver performance. The result can be a marked improvement in the SFDR of the data converter. Figure 23 shows the same converter shown earlier but with this injection of dither (ref. Figure 20). Spurious-free dynamic range is now 94 dBFS. Figure 21 and 24 show an SFDR sweep before and after adding dither. To more fully appreciate the improvement that dither can have on performance, Figures 22 and 25 show a before-and-after dither using additional data samples in the Fourier transform. Increasing to 128k sample points lowers the noise floor of the FFT; this simply makes it easier to "see" the dramatic reduction in spurious levels resulting from dither.
+15V 16k 1F NC202 NOISE DIODE (NoiseCom) 1 2 A 2.2k 3 4 REF 5 6 A 7 0.1F 8 10 9 12 11 -5V 1k 14 13 +5V 2k 16 15 LOW CONTROL (0-1 VOLT)
Processing Gain
Processing gain is the improvement in signal-to-noise ratio (SNR) gained through DSP processes. Most of this processing gain is accomplished using the channelizer chips. These special purpose DSP chips not only provide channel selection and filtering but also provide a data rate reduction. Few, if any, general purpose DSPs can accept and process data at 40.96 MSPS. The required rate reduction is accomplished through a process called decimation. The term decimation rate is used to indicate the ratio of input data rate to output data rate. For example, if the input data rate is 40.96 MSPS and the output data rate is 30 kSPS, then the decimation rate is 1365. Large processing gains may be achieved in the decimation and filtering process. The purpose of the channelizer, beyond tuning, is to provide the narrowband filtering and selectivity that traditionally has been provided by the ceramic or crystal filters of a narrowband receiver. This narrowband filtering is the source of the processing gain associated with a wideband receiver and is simply the ratio of the passband to whole band expressed in dB. For example, if a 30 kHz AMPS signal is being digitized with an AD9042 sampling at 40.96 MSPS, the ratio would be 0.030 MHz/20.48 MHz. Expressed in log form, the processing gain is -10 x log (0.030 MHz / 20.48 MHz) or 28.3 dB! Additional filtering and noise reduction techniques can be achieved through DSP techniques; many applications do use additional process gains through proprietary noise reduction algorithms.
Overcoming Static Nonlinearities with Dither
Typically, high resolution data converters use multistage techniques to achieve high bit resolution without large comparator arrays that would be required if traditional "flash" ADC techniques were employed. The multistage converter typically provides better wafer yields meaning lower cost and much lower power. However, since it is a multistage device, certain portions of the circuit are used repetitively as the analog input sweeps from one end of the converter range to the other. Although the worst DNL error may be less than an LSB, the repetitive nature of the transfer function can play havoc with low level dynamic signals. Spurious signals for a full-scale input may be -88 dBc, however 29 dB below full scale, these repetitive DNL errors may cause spurious-free dynamic range (SFDR) to fall to 80 dBc as shown in Figure 20. A common technique for randomizing and reducing the effects of repetitive static linearity is through the use of dither. The purpose of dither is to force the repetitive nature of static
OP27
OPTIONAL HIGH POWER DRIVE CIRCUIT
AD600
39
390
Figure 53. Noise Source (Dither Generator)
The simplest method for generating dither is through the use of a noise diode (Figure 53). In this circuit, the noise diode NC202 generates the reference noise that is gained up and driven by the AD600 and OP27 amplifier chain. The level of noise may be controlled by either presetting the control voltage when the system is set up, or by using a digital-to-analog converter (DAC) to adjust the noise level based on input signal conditions. Once generated, the signal must be introduced to the receiver strip. The easiest method is to inject the signal into the drive chain after the last down conversion as shown in Figure 54.
REV. A
-21-
AD9042
FROM RF/IF AIN
AD9042
VOFFSET NOISE SOURCE (REF. FIGURE 53) LPF VREF
present in the ADC bandwidth, then each must be placed 18 dB below full scale to prevent ADC overdrive. In addition, 3 dB to 15 dB should be used for ADC headroom should another signal come in-band unexpectedly. For this example, 12 dB of headroom will be allocated. Therefore we give away 30 dB of range and reduce the carrier-to-noise ratio (C/N)* to 54.8 dB. Assuming that the C/N ratio must be 6 dB or better for accurate demodulation, one of the eight signals may be reduced by 48.8 dB before demodulation becomes unreliable. At this point, the input signal power would be 40.6 V rms on the ADC input or -74.8 dBm. Referenced to the antenna, this is -104.8 dBm. To improve sensitivity, several things can be done. First, the noise figure of the receiver can be reduced. Since front end noise dominates the 0.529 mV rms, each dB reduction in noise figure translates to an additional dB of sensitivity. Second, providing broadband AGC can improve sensitivity by the range of the AGC. However, the AGC would only provide useful improvements if all in-band signals are kept to an absolute minimal power level so that AGC can be kept near the maximum gain. This noise limited example does not adequately demonstrate the true limitations in a wideband receiver. Other limitations such as SFDR are more restrictive than SNR and noise. Assume that the analog-to-digital converter has an SFDR specification of -80 dBFS or -76 dBm (Full scale = +4 dBm). Also assume that a tolerable carrier-to-interferer (C/I)** (different from C/N) ratio is 18 dB. This means that the minimum signal level is -62 dBFS (-80 plus 18) or -58 dBm. At the antenna, this is -88 dBm. Therefore, as can be seen, SFDR (single or multitone) would limit receiver performance in this example. However, as shown previously, SFDR can be greatly improved through the use of dither (Figures 22, 25). In many cases, the addition of the out-of-band dither can improve receiver sensitivity nearly to that limited by thermal noise.
Multitone Performance
Figure 54. Using the AD9042 with Dither
Receiver Example
To determine how the ADC performance relates to overall receiver sensitivity, the simple receiver in Figure 55 will be examined. This example assumes that the overall down conversion process can be grouped into one set of specifications, instead of individually examining all components within the system and summing them together. Although a more detailed analysis should be employed in a real design, this model will provide a good approximation. In examining a wideband digital receiver, several considerations must be applied. Although other specifications are important, receiver sensitivity determines the absolute limits of a radio excluding the effects of other outside influences. Assuming that receiver sensitivity is limited by noise and not adjacent signal strength, several sources of noise can be identified and their overall contribution to receiver sensitivity calculated.
GAIN = 30dB NF = 20dB BW =12.5MHz RF/IF REF IN SINGLE CHANNEL BW = 30kHz
AD9042
ENC
CHANNELIZER
DSP
40.96MHz
Figure 55. Receiver Analysis
POWER RELATIVE TO ADC FULL SCALE - dB
The first noise calculation to make is based on the signal bandwidth at the antenna. In a typical broadband cellular receiver, the IF bandwidth is 12.5 MHz. Given that the power of noise in a given bandwidth is defined by Pn = kTB, where B is bandwidth, k = 1.38 x 10-23 is Boltzman's constant and T = 300k is absolute temperature, this gives an input noise power of 5.18 x 10-14 watts or -102.86 dBm. If our receiver front end has a gain of 30 dB and a noise figure of 20 dB, then the total noise presented to the ADC input becomes -52.86 dBm (-102.86 + 30 + 20) or 0.51 mV rms. Comparing receiver noise to dither required for good SFDR, we see that in this example, our receiver supplies about 10% of the dither required for good SFDR. Based on a typical ADC SNR specification of 68 dB, the equivalent internal converter noise is 0.140 mV rms. Therefore total broadband noise is 0.529 mV rms. Before processing gain, this is an equivalent SNR (with respect to full scale) of 56.5 dB. Assuming a 30 kHz AMPS signal and a sample rate of 40.96 MSPS, the SNR through processing gain is increased by 28.3 dB to 84.8 dB. However, if 8 strong and equal signals are
The plot below shows the AD9042 in a worst case scenario of four strong tones spaced fairly close together. In this plot no dither was used, and the converter still maintained 85 dBFS of spurious-free range. As illustrated previously, a modest amount of dither introduced out-of-band could be used to lower the nonlinear components.
0
-20
ENCODE = 41 MSPS
-40
-60 3 -80 6 9 7 4 2 5 8
-100
-120 dc
4.1
8.2 12.3 FREQUENCY - MHz
16.4
20.5
Figure 56. Multitone Performance
**C/N is the ratio of signal to inband noise. **C/I is the ratio of signal to inband interferer.
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REV. A
AD9042
IF Sampling, Using the AD9042 as a Mix-Down Stage
Since performance of the AD9042 extends beyond the baseband region into the second and third Nyquist zone, the converter may find many uses as a mix down converter in both narrowband and wideband applications. Many common IF frequencies exist in this range of frequencies. If the ADC is used to sample these signals, they will be aliased down to baseband during the sampling process in much the same manner that a mixer will down-convert a signal. For signals in various Nyquist zones, the following equation may be used to determine the final frequency after aliasing.
f 1NYQUISTS = f SAMPLE - f SIGNAL f 2NYQUISTS = abs ( f SAMPLE - f SIGNAL ) f 3NYQUISTS = 2 x f SAMPLE - f SIGNAL f 4NYQUISTS = abs (2 x f SAMPLE - f SIGNAL )
RECEIVE CHAIN FOR DIGITAL BEAM-FORMING MEDICAL ULTRASOUND USING THE AD9042
The AD9042 is an excellent digitizer for digital and analog beam-forming medical ultrasound systems. The price/ performance ratio of the AD9042 allows ultrasound designers the luxury of using state-of-the-art ADCs without jeopardizing their cost budgets. ADC performance is critical for image quality. The high dynamic range and excellent noise performance of the AD9042 enable higher image quality medical ultrasound systems. Figure 58 shows the AD9042 used in one channel of the receive chain of a medical ultrasound system. The AD604 receives its input directly from the transducer, or from an external preamp connected to the transducer. The AD604 contains two separate stages. The first stage is a preamp with a fixed gain (14 dB to 20 dB) selected by a fixed resistor. The second stage is a variable gain amplifier with the gain set by the AD7226 DAC. The gain is increased over time to compensate for the attenuation of signal level in the body.
PRE-AMP 14 TO 20dB VGA -14 TO 34dB
Using the converter to alias down these narrowband or wideband signals has many potential benefits. First and foremost is the elimination of a complete mixer stage, along with amplifiers, filters and other devices, reducing cost and power dissipation. One common example is the digitization of a 21.4 MHz IF using a 10 MSPS sample clock. Using the equation above for the fifth Nyquist zone, the resultant frequency after sampling is 1.4 MHz. Figure 57 shows performance under these conditions. Even under these conditions, the AD9042 typically maintains better than 80 dB SFDR.
0 POWER RELATIVE TO ADC FULL SCALE - dB ENCODE = 10.0 MSPS AIN = 21.4MHz
TRANSDUCER/ PRE-AMP INPUT AD8041 AD604 LPF
AD9042
AD7226
Figure 58. Using the AD9042 in Ultrasound Applications
-20
-40
-60 8 -80 7 8 6 2 5 3 4
Following the AD604, a low-pass filter is used to minimize the amount of noise presented to the ADC. The AD8041 is used to buffer the filter from the AD9042 input. This function may not be required depending on the filter configuration and PC board partitioning. The digital outputs of the AD9042 are then presented to the digital system for processing.
-100
-120 dc
1.0
2.0 3.0 FREQUENCY - MHz
4.0
5.0
Figure 57. IF-Sampling a 21.4 MHz Input
REV. A
-23-
AD9042
AD9042AST OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
44-Pin Thin Quad Flatpack (ST-44)
C2080a-10-5/96
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING PLANE
1 44
0.472 (12.00) BSC SQ
34 33
TOP VIEW
(PINS DOWN)
0.393 (10.0) BSC SQ
0.006 (0.15) 0.002 (0.05) 0.008 (0.20) 0.003 (0.09)
11
23 12 22
0.039 (1.00) REF
0.031 (0.80) BSC
0.018 (0.45) 0.012 (0.30)
AD9042AD OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Hermetic Ceramic DIP (DH-28)
28 15
0.595 0.010 (15.11 0.25)
1 14
PIN 1 IDENTIFIERS 0.225 (5.72) MAX
1.400 0.014 (35.56 0.35)
0.050 0.010 (1.27 0.25) 0.150 (3.81) MIN
0.010 0.002 (0.25 0.05) 0.600 (15.24) REF
0.018 0.002 (0.46 0.05)
0.100 (2.54) 0.05 (1.27) TYP TYP
SEATING PLANE
-24-
REV. A
PRINTED IN U.S.A.

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